The present invention is related to the field of microprocessor design and, more particularly, to the design of shifter units used in microprocessors.
Data bits shifting is a common operation in a microprocessor design by which bits of a data word are shifted into lower order bit positions (shift right) or into higher order bit positions (shift left). However, a shifter unit is a troublesome circuit block in a microprocessor design because wide data bus is generally needed for connecting different components in the shifter unit.
The problem is further complicated when the shifter unit is required to handle both the data word shifting and rotating functions. For example, in the Intel x86 instruction set, there contains two groups of instructions (i.e. shift group, and rotate group instructions) that require either shifting or rotating function.
According to the Intel (TM) x86 instruction set, the shift instruction shifts the bits of the first operand (i.e. destination operand) to the left or right by the number of bits specified in the second operand (i.e. count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF flag, then discarded. Finally, at the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand. According to the Intel instruction set, the destination operand can be a register or a memory location. The count operand can be an immediate value or register CL. For a 32-bit data, the count is masked to 5 bits, which limits the count range to 0 to 31.
According to the Intel (TM) instruction set, the shift arithmetic left (SAL) and shift logic left (SHL) instructions perform the same operation; they shift the bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared.
The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction type. The SHR instruction clears the most significant bit; the SAR instruction sets or clears the most significant bit to correspond to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills the empty bit position's shifted value with the sign of the unshifted value.
The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides the value by 2.
The double precision shift left (SHLD) shifts the first operand (destination operand) to the left the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting with bit 0 of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign changed occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.
Similarly, the double precision shift right (SHRD) shifts the first operand (destination operand) to the right the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with the most significant bit of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be an immediate byte or the contents of the CL register. If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, the flags are not affected.
The rotate instruction shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. The processor restricts the count to a number between 0 and 31 by masking all the bits in the count operand except the least-significant bits.
The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most significant bit, which is rotated to the least significant bit location. The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant positions, except for the least significant bit, which is rotated to the most significant bit location.
The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least significant bit and shifts the most significant bit into the CF flag. The RCR instruction shifts the CF flag into the most significant bit and shifts the least significant bit into the CF flag. For the ROL and ROR instructions, the original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.
Therefore, it is desirable to have a universal shifter unit capable of handling both the shift and rotate functions, while being able to maintain simple layout and routing designs.